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HM62W8128B Series
131,072-word x 8-bit High Speed CMOS Static RAM
ADE-203-656A (Z) Rev. 1.0 Oct. 14, 1996
Description
The Hitachi HM62W8128B is a CMOS static RAM organized 131,072-word x 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 m Hi-CMOS shrink process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. The device, packaged in a 525-mil SOP (460-mil body SOP) or a 8 mm x 20 mm TSOP with thickness of 1.2 mm, is available for high density mounting. TSOP package is suitable for cards, and reverse type TSOP is also provided.
Features
* * * Single 3.3 V supply Fast access time: 100/120 ns (max) Power dissipation: Active: 23 mW/MHz (typ) Standby: 4 W (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Directry CMOS compatible all inputs and outputs. Capability of battery backup operation. 2 chip selection for battery backup
* * * * *
HM62W8128B Series
Ordering Information
Type No. HM62W8128BLFP-10 HM62W8128BLFP-12 HM62W8128BLFP-10SL HM62W8128BLFP-12SL HM62W8128BLT-10 HM62W8128BLT-12 HM62W8128BLT-10SL HM62W8128BLT-12SL HM62W8128BLR-10 HM62W8128BLR-12 HM62W8128BLR-10SL HM62W8128BLR-12SL Access time 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 100 ns 120 ns 8 mm x 20 mm 32-pin TSOP (reverse-bend type) (TFP-32DR) 8 mm x 20 mm 32-pin TSOP (normal-bend type) (TFP-32D) Package 525-mil 32-pin plastic SOP (FP-32D)
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HM62W8128B Series
Pin Arrangement
HM62W8128BLT Series (Normal Type TSOP)
A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3
HM62W8128BLFP Series NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3
(Top view) HM62W8128BLR Series (Reverse Type TSOP)
A4 A5 A6 A7 A12 A14 A16 NC VCC A15 CS2 WE A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CS1 A10 OE
(Top view)
Pin Description
Pin name A0 to A16 I/O0 to I/O7 CS1 CS2 WE OE NC VCC VSS Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable No connection Power supply Ground
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HM62W8128B Series
Block Diagram
LSB V CC V SS
* * * * *
A8 A13 A4 A5 A6 A7 A12 A14 A15 Row decoder
Memory matrix 512 x 2,048
MSB
I/O0 Input data control I/O7
* *
Column I/O Column decoder
* *
LSB A0 A1 A2 A3 A10 A11 A9 A16 MSB
* *
CS2 CS1 WE OE
Timing pulse generator Read/Write control
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HM62W8128B Series
Function Table
WE x x H H L L CS1 H x L L L L CS2 x L H H H H OE x x H L H L Mode Standby Standby Output disable Read Write Write VCC current I SB , I SB1 I SB , I SB1 I CC I CC I CC I CC I/O pin High-Z High-Z High-Z Dout Din Din Ref. cycle -- -- -- Read cycle Write cycle (1) Write cycle (2)
Note: x: H or L
Absolute Maximum Ratings
Parameter Power supply voltage* Terminal voltage*
1 1
Symbol VCC VT PT Topr Tstg Tbias
Value -0.5 to + 4.6 -0.5* to V CC + 0.3* 1.0 0 to +70 -55 to +125 -10 to 85
2 3
Unit V V W C C C
Power dissipation Operating temperature Storage temperature Storage temperature under bias
Notes: 1. Relative to VSS 2. VT min: -3.0 V for pulse half-width 30 ns 3. Maximum voltage is 4.6 V
Recommended DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC VSS Input voltage VIH VIL Note: Min 3.0 0 2.0 -0.3 *
1
Typ 3.3 0 -- --
Max 3.6 0 VCC + 0.3 0.8
Unit V V V V
1. VIL min: -3.0 V for pulse half-width 30 ns
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HM62W8128B Series
DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO | -- -- Typ*1 -- -- Max 1 1 Unit A A Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, VI/O = VSS to V CC CS1 = VIL, CS2 = VIH, Others = VIH/V IL, I I/O = 0 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/V IL
Operating power supply current: DC
I CC
-- --
6 22
10 30
mA mA
Operating HM62W8128B-10 I CC1 power supply current HM62W8128B-12 I CC1 I CC2
-- --
20 7
25 10 mA Cycle time = 1 s, duty = 100%, I I/O = 0 mA, CS1 0.2 V, CS2 V CC - 0.2 V VIH V CC - 0.2 V, VIL 0.2 V (1) CS1 = VIH, CS2 = VIH or (2) CS2 = VIL 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1 V CC - 0.2 V, CS2 V CC - 0.2 V
Standby power supply current: DC Standby power supply current (1): DC
I SB I SB1
-- --
0.5 1.2*2
1 70* 2
mA A
I SB1 Output voltage VOL
-- -- --
1.2*3 -- -- --
30* 3 0.4 0.2 -- --
A V V V V I OL = 2 mA I OL = 100 A I OH = -2 mA I OH = -100 A
VOH
2.4
VCC - 0.2 --
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25C and not guaranteed. 2. This characteristic is guaranteed only for L version. 3. This characteristic is guaranteed only for L-SL version.
Capacitance (Ta = 25C, f = 1.0 MHz)
Parameter Input capacitance*
1 1
Symbol Cin CI/O
Min -- --
Typ -- --
Max 8 10
Unit pF pF
Test conditions Vin = 0 V VI/O = 0 V
Input/output capacitance* Note:
1. This parameter is sampled and not 100% tested.
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HM62W8128B Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, unless otherwise noted.)
Test Conditions * * * * * Input pulse levels: 0.4 V to 2.4 V Input rise and fall time: 5 ns Input timing reference levels: 1.4 V output timing reference levels: 2.0 V/0.8 V Output load (Including scope and jig)
Read Cycle
,,, , , ,, ,
500 Dout 50 pF 1.4 V HM62W8128B -10 -12 Max -- 100 100 100 50 -- -- -- 35 35 35 -- Min 120 -- -- -- -- 10 10 5 0 0 0 10 Max -- 120 120 120 60 -- -- -- 40 40 40 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 1, 2, 3 2, 3 1, 2, 3 2, 3 Notes Symbol t RC t AA t CO1 t CO2 Min 100 -- -- -- -- 10 10 5 0 0 0 10 t OE t LZ1 t LZ2 t OLZ t HZ1 t HZ2
Parameter Read cycle time Address access time Chip selection to output valid
Output enable to output valid Chip selection to output in low-Z
Output enable to output in low-Z Chip deselection to output in high-Z
Output disable to output in high-Z Output hold from address change
t OHZ t OH
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HM62W8128B Series
Write Cycle
HM62W8128B -10 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Symbol t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW Min 100 80 0 80 60 0 0 40 0 5 0 Max -- -- -- -- -- -- 35 -- -- -- 35 -12 Min 120 85 0 85 65 0 0 45 0 5 0 Max -- -- -- -- -- -- 40 -- -- -- 40 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 8 4, 13 7 1, 2, 8 5 6 Notes
Output disable to output in High-Z t OHZ
Notes: 1. t HZ , t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle. 8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 9. If CS1 goes low simultaneously with WE going low or after WE going low, the outputs remain in a high impedance state. 10. Dout is the same phase of the latest written data in this write cycle. 11. Dout is the read data of next address. 12. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP tDW min + tWHZ max
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HM62W8128B Series
Timing Waveform
Read Timing Waveform (WE = VIH)
t RC
Address
Address Valid t AA
CS1 t CO1 t LZ1 CS2 t CO2 t LZ2 t HZ2 t HZ1
OE t OE t OLZ Dout High Impedance t OHZ t OH Data Valid
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HM62W8128B Series
Write Timing Waveform (1) (OE Clock)
t WC Address Address Valid t AW OE t CW
CS1
*9
t WR
CS2 t AS WE t OHZ High Impedance Dout t DW Din t DH t WP
Data Valid
10
HM62W8128B Series
Write Timing Waveform (2) (OE Low Fixed)
t WC Address
Address Valid t CW t WR
CS1
*9
CS2
t AW t WP WE t AS t WHZ t OW
*10 *11
t OH
Dout
High Impedance t DW t DH
*12
Din
Data Valid
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HM62W8128B Series
Low VCC Data Retention Characteristics (Ta = 0 to +70C)
Parameter VCC for data retention Symbol VDR Min 2.0 Typ* 4 Max -- -- Unit V Test conditions*3 Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V CS1 V CC - 0.2 V VCC = 3.0 V, Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V, CS1 V CC - 0.2 V
Data retention current
I CCDR (L version)
--
1
50*1
A
I CCDR (L-SL version) Chip deselect to data retention time Operation recovery time t CDR tR
-- 0 5
1 -- --
15*2 -- --
A ns ms See retention waveform
Notes: 1. This characteristic is guaranteed only for L version, 20 A max. at Ta = 0 to 40C. 2. This characteristic is guaranteed only for L-SL version, 3 A max. at Ta = 0 to 40C. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 V CC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed.
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HM62W8128B Series
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
t CDR V CC 3.0 V
Data retention mode
tR
2.0 V V DR1 CS1 0V CS1 VCC - 0.2 V
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR V CC 3.0 V CS2 V DR2 0.4 V 0V
Data retention mode
tR
0 V < CS2 < 0.2 V
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HM62W8128B Series
Package Dimensions
HM62W8128BLFP Series (FP-32D)
20.45 20.95 Max 32 17
11.7 Max
Unit: mm
1 1.0 Max
14.14 0.30 16
3.0 Max
+ 0.13 - 0.07
1.42
0.22
1.27
0.10 0.40 + 0.05 -
0.10 0.15 M
0.05 Min
0-8 0.8
HM62W8128BLT Series (TFP-32D)
8.0 8.2 Max 32
Unit: mm
17
1
16 0.5
0.2 0.1
0.08 M 20.0 0.2 0.45 Max 0-5
0.08 Min 0.18 Max
1.2 Max
18.4 0.17 0.05
0.10
0.5 0.1
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HM62W8128B Series
Package Dimensions (cont.)
HM62W8128BLR Series (TFP-32DR)
Unit: mm
8.0 8.2 Max 17
32
16
1 0.50
0.20 0.10
0.08 M 20.0 0.2 0.45 Max
18.40
1.20 Max
0-5 0.17 0.05 0.10 0.08 Min 0.18 Max
0.50 0.10
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HM62W8128B Series
When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207
Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00
Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322
Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071
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HM62W8128B Series
Revision Record
Rev. 1.0 Date Oct. 14, 1996 Contents of Modification Initial issue Drawn by Approved by
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